A Multi-FPGA Rapid Prototyping System with the Reusable AES Core

Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette

FPGA Based Low Cost Generic Reusable Module for the Rapid Prototyping of Subsystems

The development of a model for subsystem reuse and the evaluation of currently available rapid prototyping platforms has prompted the development of a GEneric Reusable Module (GERM). The GERM is a low-cost, stand-alone, reprogrammable development tool designed for prototyping reusable subsystems. The GERM, and associated templates, aid the designer in rapidly prototyping and reusing subsystem d...

Rapid prototyping of Networks-on-Chip on multi-FPGA platforms

Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We pres...

Dual CLEFIA/AES Cipher Core on FPGA

In this paper a compact high throughput dual-cipher hardware structure is proposed, supporting the novel CLEFIA algorithm and the encryption standard AES. Currently, the more efficient and dedicated structures only allow to process the CLEFIA or the AES encryption algorithms. On the other hand, the existing multi-algorithm processors impose significantly higher area costs and are not able to ac...

Rapid Prototyping of an FPGA-Based Video Processing System